1. Field of the Invention
The present invention relates to an edge enhancement circuit for enhancing the edge of an image. Specifically, this invention relates to an edge enhancement circuit wherein pixel data used for filter processing for obtaining an edge-enhanced signal are placed at one-pixel intervals with respect to pixel data about a main-line signal to thereby reduce required memory capacity and power consumption.
2. Description of the Related Art
An analog system and a digital system are known as systems for enhancing the contour or edge of an image. In the analog system, a method for separately creating edge-enhanced signals in horizontal and vertical directions and adding these edge-enhanced signals to a main-line signal has heretofore been used. It was however necessary to accurately fit the amounts of delays of the respective signals to one another and perform their adjustments using parts such as delay lines or the like.
In the digital system on the other hand, an edge-enhanced signal added to a certain pixel is determined by calculation from the difference in level between the certain pixel and each pixel lying around the certain pixel. Therefore, edge-enhanced signals including a horizontal direction, a vertical direction and a slanting direction are obtained at a time. Thus, the adjustments for accurately fitting the amounts of delays of the respective signals to one another as in the aforementioned analog system become unnecessary.
FIG. 1 shows a configuration of a digital edge enhancement circuit 100. The edge enhancement circuit 100 has a signal input terminal 101 to which an analog video signal NVa to be edge-enhanced is inputted, and a clock input terminal 102 to which a clock signal CLKN is inputted. When, in this case, the video signal NVa is an NTSC video signal, for example, the frequency of the clock signal CLKN is set to 4 fsc (fsc: chrominance sub-carrier frequency).
The edge enhancement circuit 100 also has an A/D converter 103 for sampling the analog video signal NVa, based on the clock signal CLKN to thereby obtain a digital video signal NVb, a delay line 104 for delaying the video signal NVb by one horizontal period (1H) to thereby obtain a video signal NVc, and a delay line 105 for further delaying the video signal NVc by one horizontal period (1H) to thereby obtain a video signal NVd. The delay lines 104 and 105 are respectively made up of an FIFO (first-in first-out) memory, for example.
Further, the edge enhancement circuit 100 has a digital filter 106 for performing filter processing using the video signals NVb, NVc and NVd to thereby obtain a digital edge-enhanced signal NIEa. The digital filter 106 performs the following operation to form or create the edge-enhanced signal NIEa. That is, FIG. 2A shows nine pixel data (sampled data) used for the operation. P00, P01 and P02 indicate pixel data constituting the video signal NVd, P10, P11, and P12 indicate pixel data constituting the video signal NVc, and P20, P21, and P22 indicate pixel data constituting the video signal NVb. FIG. 2B shows operators for the respective pixel data. Here, P11, becomes a pixel to be noted for obtaining the edge-enhanced signal NIEa. The edge-enhanced signal NIEa with respect to P11, is determined from the following equation (1):
NIEa=8xc3x97P11xe2x88x92(P00+P01+P02+P10+P12+P20+P21+P22)xe2x80x83xe2x80x83(1)
Moreover, the edge enhancement circuit 100 has a D/A converter 107 for converting the edge-enhanced signal NIEa to an analog signal so as to obtain an analog edge-enhanced signal NIEb, a D/A converter 108 for converting the video signal NVc outputted from the delay line 104 to an analog signal as a main-line signal so as to obtain an analog video signal NVe, an adder 109 for adding the edge-enhanced signal NIEb to the video signal NVe to thereby obtain an edge-enhanced analog video signal NVf, and a signal output terminal 110 for outputting the video signal NVf therefrom.
Incidentally, the delay lines 104 and 105, the digital filter 106, and the D/A converters 107 and 108 are supplied with the clock signal CLKN as an operating clock.
The operation of the edge enhancement circuit 100 shown in FIG. 1 will be described.
The analog video signal NVa inputted to the signal input terminal 101 is supplied to the A/D converter 103 where it is sampled based on the clock CLKN so as to be converted to the digital video signal NVb. The video signal NVb is delayed by one horizontal period by the delay line 104 to obtain the video signal NVc. The video signal NVc is further delayed by one horizontal period by the delay line 105 to obtain the video signal NVd. These video signals NVb through NVd are supplied to the digital filter 106 where the filter processing using the video signals NVb through NVd is performed to form the digital edge-enhanced signal NIEa.
Further, the video signal NVc outputted from the delay line 104 is supplied to the D/A converter 108 where it is converted to the analog signal, whereby the analog video signal NVe is obtained as the main-line signal. Similarly, the edge-enhanced signal NIEa outputted from the filter 106 is supplied to the D/A converter 107 where it is converted to the analog signal, whereby the analog edge-enhanced signal NIEb is obtained. Further, the video signal NVe and the edge-enhanced signal NIEb are supplied to the adder 109 where they are added together to obtain the edge-enhanced analog video signal NVf. The resultant video signal NVf is drawn from the adder 109 to the signal output terminal 110.
Since the frequency of the clock signal CLKN is low when the analog video signal NVa inputted to the signal input terminal 101 is an ordinary video signal such as an NTSC video signal or the like, the edge enhancement circuit 100 shown in FIG. 1 offers no problem. However, the edge enhancement circuit has a drawback in that when the analog video signal NVa is a hi-vision video signal, the frequency of the clock signal CLKN becomes high to increase the capacity of the FIFO memory constituting each of the delay lines 104 and 105, and since the basic clock used for the computation of the digital filter 106 becomes high-speed, power consumption greatly increases. When a hi-vision signal having 2200 pixels/line, for example, is edge-enhanced, the frequency of the clock signal CLKN results in 74.25 MHz. Further, the FIFO memory constituting each of the delay lines 104 and 105 needs a capacity of 2200 words xc3x978 bits per one (with the quantization of the A/D converter and D/A converter being performed as 8 bits) and an access speed of about 10 ns.
With the foregoing in view, it is therefore an object of the present invention to provide an edge enhancement circuit capable of reducing required memory capacity and power consumption when, for example, a hi-vision signal is edge-enhanced.
According to one aspect of the invention, for achieving the above object, there is provided an edge enhancement circuit, comprising first analog/digital converting means for sampling an input analog video signal, based on a first clock signal to thereby obtain a first digital video signal, filter processing means for filter-processing the first digital video signal to thereby obtain a digital edge-enhanced signal, second analog/digital converting means for sampling the input analog video signal, based on a second clock signal identical in frequency to the first clock signal and kept in inverse phase with each other to thereby obtain a second digital video signal, switch means for alternately taking out pixel data (sampled data) constituting the first and second digital video signals, based on a third clock signal having a frequency corresponding to twice that of the first clock signal to thereby obtain a digital main-line signal, and signal adding means for adding the signal outputted from the filter processing means to the signal outputted from the switch means to thereby obtain an edge-enhanced output video signal. Further, the edge enhancement circuit further comprises digital/analog converting means for converting the digital edge-enhanced signal to an analog edge-enhanced signal and supplying the same to the signal adding means.
According to the present invention, the input analog video signal is sampled based on the first clock signal so as to be converted to the first digital video signal. The first digital video signal is subjected to filter processing to obtain the digital edge-enhanced signal.
Further, the input analog video signal is sampled based on the second clock signal identical in frequency to the first clock signal and kept in inverse phase with the first clock signal so as to be converted to the second digital video signal. The pixel data constituting the first and second digital video signals are alternately taken out based on the third clock signal having the frequency corresponding to twice that of the first clock signal to obtain the digital main-line signal.
Since, in this case, the second clock signal is identical in frequency to the first clock signal and held in inverse phase with the first clock signal, the pixel data constituting the second digital video signal results in one sampled between the pixel data constituting the first digital video signal.
Therefore, the above-described digital main-line signal becomes equivalent to the digital video signal obtained by sampling the input analog video signal, based on the third clock signal. If the pixel data (sampled data) constituting the digital main-line signal is set as the reference, then the pixel data used for the filter processing for obtaining the above-described edge-enhanced signal are set at one-pixel intervals. Incidentally, if it is considered that while the hi-vision signal has a signal band of 30 MHz, the enhancement of the neighborhood of 20 MHz as the center is effective in improving image quality by edge enhancement, then one-pixel intervals are enough for the pixel data used for the filter processing for obtaining the edge-enhanced signal.
Further, the above-described digital main-line signal and digital edge-enhanced signal are converted to the analog signals respectively. Thereafter, they are added together to obtain the edge-enhanced output analog video signal.
When a hi-vision signal having 2200 pixels/line, for example, is edge-enhanced, the frequencies of the first and second clock signals result in 37.125 MHz respectively and the frequency of the third clock signal results in 74.25 MHz. Since, in this case, the filter processing means is activated based on the clock signal of 37.125 MHz, the required memory capacity may be xc2xd and power consumption is also greatly reduced, as compared with one activated based on the clock signal of 74.25 MHz.
Incidentally, the first and second clock signals may be respectively reversed in phase for each field. Thus, even if the pixel data (sampled data) used for the filter processing for obtaining the edge-enhanced signal are set at one-pixel intervals with the pixel data about the main-line signal as the reference, an edge-enhanced image whose sloping edge portion is smooth, can be obtained by an integral effect.
Typical ones of various inventions of the present inventions have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.
While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:
FIG. 1 is a block diagram showing one example of a digital edge enhancement circuit;
FIGS. 2A and 2B are respectively diagrams illustrating one example of correspondences between pixel data and operators used in a digital filter;
FIG. 3 is a block diagram showing a configuration of an edge enhancement circuit according to a first embodiment of the present invention;
FIG. 4 is a diagram illustrating an arrangement of pixel data (sampled data) employed in the first embodiment;
FIGS. 5A through 5E are respectively diagrams for describing the manner in which sloping edge portions of images employed in the first embodiment are seen;
FIG. 6 is a block diagram depicting a configuration of an edge enhancement circuit according to a second embodiment of the present invention;
FIG. 7 is a diagram showing an arrangement of pixel data (sampled data) employed in the second embodiment; and
FIGS. 8A through 8E are respectively diagrams for describing the manner in which sloping edge portions of images employed in the second embodiment are seen.